Semiconductor devices and more particularly integrated circuits (IC) are very sensitive to high voltages that may be generated by an electrostatic discharge (ESD) event. For example, an ESD event can lead to pulses of high current (several amperes) of a short duration within an IC, which can lead to failure of the IC. For this reason, ESD protection circuitry is essential to ensure that ICs are not destroyed during an ESD event.
Silicon controlled rectifiers (SCR) in BULK silicon technologies are known to protect an IC against over-voltage conditions, e.g., ESD events. In known implementations, the SCR protection devices have been incorporated within the circuitry to provide a discharge path for the high current produced by the discharge of the high electrostatic potential. For example, once the ESD event is detected, the SCR changes to a conductive state to shunt the current to ground, the conductive state is maintained until the voltage is discharged to a safe level.
SCR technology has been implemented very successfully in BULK technologies; however, new integration schemes are needed for implementation in silicon-on-insulator (SOI) technologies. For example, in SOI technologies, the SCRs are formed directly on an insulator layer, which effectively isolates the SCR pwells which the cathodes are formed in one another when parallel fingers exist. This leads to uncoupled clamps (pwells) such that upon a high current ESD event, only a limited number (e.g., single) of N+ diffusion cathodes turn on, while the remaining N+ diffusion cathodes remain turned off. This results in an unstable device which exhibits weak ESD performance.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.